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general description the max8543/max8544 current-mode, constant-fre- quency pwm buck controllers operate from a 3v to 13.2v input supply and generate adjustable 0.8v to 0.9 x v in output voltages at loads up to 25a. they feature adjustable switching frequency and synchronization for noise-sensitive applications. the max8543/max8544 can start with (or without) a pre- existing bias on the output, without discharging the out- put. this feature simplifies tracking supply designs for core and i/o applications and redundant supply designs. the max8543/max8544 use the dc resistance of the output inductor as the current-sense element for loss- less, low-cost current sensing. the current-sense threshold can be set to four discrete levels to accom- modate inductors with different dc resistance values. the max8544 features a power-ok monitor and two max8544 controllers that can operate at 180 out-of- phase for dual-output applications. applications base stations networks and telecom storage servers features ? prebias startup/monotonic ? 1% output accuracy ? ceramic, polymer, or electrolytic capacitors ? 200khz to 1mhz adjustable frequency ? 160khz to 1.2mhz synchronization ? lossless, foldback current limit ? overvoltage protection ? enable (on/off) ? adjustable soft-start ? max8544 latch-off/autorecovery power-ok monitor out-of-phase clock output max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp ________________________________________________________________ maxim integrated products 1 ordering information max8543 on optional synchronization off bst vl v in = 3v to 5.5v comp ilim fsync en ss pgnd gnd in dh lx dl cs+ cs- fb input 3v to 13.2v output 0.8v to 0.9 x v in up to 25a pok (max8544) typical operating circuit 19-3155; rev 0; 5/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package max8543 eee -40? to +85? 16 qsop max8544 eep -40? to +85? 20 qsop pin configurations appear at end of data sheet.
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = 13.2v, v bst - v lx = 5v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, en, cs+, cs- to gnd .......................................-0.3v to +14v bst, dh to lx ..........................................................-0.3v to +6v bst to gnd ............................................................-0.3v to +20v dl, comp, ilim2, ss, synco, fsync to gnd .......................................-0.3v to (v vl + 0.3v) vl, fb, pok, ilim1, ilim, mode to gnd ................-0.3v to +6v pgnd to gnd .......................................................-0.3v to +0.3v continuous power dissipation (t a = +70 c) 16-pin qsop (derate 8.3mw/? above +70?) .......666.7mw 20-pin qsop (derate 9.1mw/? above +70?) .......727.3mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter conditions min typ max units operating input voltage range vl connected to in for v in < 5.5v 3.0 13.2 v quiescent supply current v fb = 0.9v, no switching 2 3 ma en = gnd, mode = gnd, in not connected to vl 10 shutdown supply current en = gnd, vl = in, mode = gnd 20 ? vl undervoltage-lockout trip level v vl rising, typical hysteresis is 80mv 2.52 2.7 2.88 v output voltage adjust range (v out ) (note 1) 0.8 v vl output voltage 5.5v < v in < 13.2v, 1ma < i vl < 75ma 4.5 5 5.5 v vl output current 75 ma voltage reference ss shutdown resistance from ss to gnd, v en = 0v 20 100 ? ss soft-start current v ref = 0.625v 14 24 34 ? soft-start ramp time output from 0% to 100%, c ref = 0.01? to 1? 33 ms/? error amplifier fb regulation voltage 0.792 0.8 0.808 v transconductance 70 110 160 ? comp shutdown resistance from comp to gnd, v en = 0v 20 100 ? fb input leakage current v fb = 0.9v 5 100 na fb input common-mode range -0.1 +0.9 v current-sense amplifier v ilim1 = 0v 8.8 11 13.2 v ilim1 = (1/3)v vl 4.8 6 7.2 v ilim1 = (2/3)v vl 3.2 4 4.8 voltage gain v out = 0 to 13v v ilim1 = v vl 2.4 3 3.6 v / v current limit ilim2 output current (max8544 only) r ilim2 = 50k ? to 200k ? 4.5 5 5.5 ? ilim1 input current v ilim1 = 0v or v vl -1 +1 ?
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in = 13.2v, v bst - v lx = 5v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter conditions min typ max units v cs+ - v cs- , v ilim1 = 0v 38.5 50 56.5 v cs+ - v cs- , v ilim1 = (1/3)v vl 85 100 115 v cs+ - v cs- , v ilim1 = (2/3)v vl 127.5 150 172.5 v cs+ - v cs- , v ilim1 = v vl 170 200 230 v lx - v pgnd , r ilim2 = 50k ? (max8544 only) -42.5 -50 -57.5 v lx - v pgnd , r ilim2 = 200k ? (max8544 only) -160 -200 -240 v lx - v pgnd , v fb = 0.8v (max8543 only) -110 -130 -150 current-limit threshold v lx - v pgnd , v fb = 0v (max8543 only) -20 -30 -40 mv negative current-limit threshold % of positive-direction current limit v lx - v pgnd -25 -50 -85 % cs+, cs- input current v cs+ = v cs- = 0 or 5v -40 +40 ? cs+, cs- input common-mode range 0 13.2 v oscillator r fsync = 18.2k ? 800 1000 1200 switching frequency r fsync = 158k ? 200 khz minimum off-time measured at dh 150 220 270 ns minimum on-time measured at dh 90 145 ns fsync synchronization range 160 1200 khz fsync input high pulse width 100 ns fsync input low pulse width 100 ns fsync rise/fall time 100 ns synco phase shift from dh rising r fsync = 18.2k ? , free-running mode, at maximum duty cycle 165 180 195 degrees synco output low level i synco = 5ma 0.4 v synco output high level i synco = 5ma v vl - 1v v mosfet drivers (v bst - v lx ) = 5v 1 2.5 dh on-resistance, high state (v bst - v lx ) = 3v 1.2 ? (v bst - v lx ) = 5v 1 2.5 dh on-resistance, low state (v bst - v lx ) = 3v 1.2 ? v vl = 5v 1 2.5 dl on-resistance, high state v vl = 3v 1.2 ? v vl = 5v 0.6 1.7 dl on-resistance, low state v vl = 3v 0.8 ? low-side off to high-side on 55 break-before-make dead time high-side off to low-side on 40 ns lx, bst, in leakage current v bst = 18.7v, v lx = 13.2v, v in = 13.2v 5 ? thermal protection thermal shutdown rising temperature +160 ? thermal-shutdown hysteresis 15 ?
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp 4 _______________________________________________________________________________________ electrical characteristics (continued) (v in = 13.2v, v bst - v lx = 5v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter conditions min typ max units pok power-ok threshold v fb rising, percent of v out , typical hysteresis is 3% 88 91 94 % pok output voltage, low v fb = 0.6v, i pok = 2ma 25 200 mv pok leakage current, high v pok = 5.5v 0.001 1 ? overvoltage protection (ovp) output overvoltage fault-trip level rising edge compared to regulation set point; triggers after one or two clock cycles +110 +115 +120 % mode control mode logic-level low 3v v vl 5.5v 0.4 v mode logic-level high 3v v vl 5.5v 1.8 v v mode = 0v -1 +1 mode input current mode = vl 5 10 ? shutdown control en logic-level low 3v v vl 5.5v 0.45 v en logic-level high 3v v vl 5.5v 2 v v en = 0 or 5.5v -1 +4 en input current v en = 13.2v 1.5 6 ? electrical characteristics (v in = 13.2v, v bst - v lx = 5v, t a = -40? to +85? , unless otherwise noted.) (note 2) parameter conditions min max units operating input voltage range vl connected to in for v in < 5.5v 3.0 13.2 v quiescent supply current v fb = 0.9v, no switching 3 ma en = gnd, mode = gnd, in not connected to vl 10 shutdown supply current en = gnd, vl = in, mode = gnd 20 ? vl undervoltage-lockout trip level v vl rising, typical hysteresis is 80mv 2.52 2.88 v output voltage adjust range (v out ) (note 1) 0.8 v vl output voltage 5.5v < v in < 13.2v, 1ma < i vl < 75ma 4.5 5.5 v vl output current 75 ma voltage reference ss shutdown resistance from ss to gnd, v en = 0v 100 ? ss soft-start current v ref = 0.625v 14 34 ? error amplifier fb regulation voltage 0.788 0.808 v transconductance 70 160 ? comp shutdown resistance from comp to gnd, v en = 0v 100 ? fb input leakage current v fb = 0.9v 100 na fb input common-mode range -0.1 +0.9 v
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp _______________________________________________________________________________________ 5 electrical characteristics (continued) (v in = 13.2v, v bst - v lx = 5v, t a = -40? to +85? , unless otherwise noted.) (note 2) parameter conditions min max units current-sense amplifier v ilim1 = 0v 8.8 13.2 v ilim1 = (1/3)v vl 4.8 7.2 v ilim1 = (2/3)v vl 3.2 4.8 voltage gain v out = 0 to 13v v ilim1 = v vl 2.4 3.6 v / v current limit ilim2 output current (max8544 only) r ilim2 = 50k ? to 200k ? 4.2 5.5 ? ilim1 input current v ilim1 = 0v or v vl -1 +1 ? v cs+ - v cs- , v ilim1 = 0v 38.5 56.5 v cs+ - v cs- , v ilim1 = (1/3)v vl 85 115 v cs+ - v cs- , v ilim1 = (2/3)v vl 127.5 172.5 v cs+ - v cs- , v ilim1 = v vl 170 230 v lx - v pgnd , r ilim2 = 50k ? (max8544 only) -40 -60 v lx - v pgnd , r ilim2 = 200k ? (max8544 only) -160 -240 v lx - v pgnd , v fb = 0.8v (max8543 only) -110 -150 current-limit threshold v lx - v pgnd , v fb = 0v (max8543 only) -20 -40 mv negative current-limit threshold % of positive-direction current limit v lx - v pgnd -25 -85 % cs+, cs- input current v cs+ = v cs- = 0v or 5v -40 +40 ? cs+, cs- input common-mode range 0 13.2 v oscillator switching frequency r fsync = 18.2k ? 800 1200 khz minimum off-time measured at dh 150 270 ns minimum on-time measured at dh 140 ns fsync synchronization range 160 1200 khz fsync input high pulse width 100 ns fsync input low pulse width 100 ns fsync rise/fall time 100 ns synco phase shift from dh rising r fsync = 18.2k ? 165 195 degrees synco output low level i synco = 5ma 0.4 v synco output high level i synco = 5ma v vl - 1v v mosfet drivers dh on-resistance, high state (v bst - v lx ) = 5v 2.5 ? dh on-resistance, low state (v bst - v lx ) = 5v 2.5 ? dl on-resistance, high state v vl = 5v 2.5 ? dl on-resistance, low state v vl = 5v 1.7 ? lx, bst, in leakage current v bst = 18.7v, v lx = 13.2v, v in = 13.2v 5 ?
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp 6 _______________________________________________________________________________________ electrical characteristics (continued) (v in = 13.2v, v bst - v lx = 5v, t a = -40? to +85? , unless otherwise noted.) (note 2) parameter conditions min max units pok power-ok threshold v fb rising, percent of v out , typical hysteresis is 3% 88 94 % pok output voltage, low v fb = 0.6v, i pok = 2ma 200 mv pok leakage current, high v pok = 5.5v 1 ? overvoltage protection (ovp) output overvoltage fault-trip level rising edge compared to regulation set point; triggers after one or two clock cycles +110 +120 % mode control mode logic-level low 3v v vl 5.5v 0.4 v mode logic-level high 3v v vl 5.5v 1.8 v v mode = 0v -1 +1 mode input current mode = vl 10 ? shutdown control en logic-level low 3v v vl 5.5v 0.45 v en logic-level high 3v v vl 5.5v 2 v v en = 0v or 5.5v -1 +4 en input current v en = 13.2v 6 ? note 1: maximum output voltage is limited by maximum duty cycle and external components. note 2: specifications to -40? are guaranteed by design and not production tested.
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp _______________________________________________________________________________________ 7 efficiency vs. load current with 12v input max8543 toc01 load current (a) efficiency (%) 10 1 10 20 30 40 50 60 70 80 90 100 0 0.1 100 v out = 3.3v v out = 2.5v v out = 1.8v f s = 600khz efficiency vs. load current with 3.3v input max8543 toc02 load current (a) efficiency (%) 10 1 10 20 30 40 50 60 70 80 90 100 0 0.1 100 v out = 2.5v v out = 1.8v f s = 500khz v out = 1.5v load regulation with 12v input max8543 toc03 load current (a) output voltage (v) 12 9 6 3 2.46 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 2.45 015 line regulation with 12v input and 2.5v output max8543 toc04 input voltage (v) output voltage (v) 12.6 12.0 11.4 2.492 2.494 2.496 2.498 2.500 2.502 2.504 2.506 2.508 2.510 2.490 10.8 13.2 no load 15a load line regulation 3.0v to 3.6v input max8543 toc05 input voltage (v) output voltage (v) 3.5 3.4 3.3 3.2 3.1 2.44 2.46 2.48 2.50 2.52 2.54 2.42 3.0 3.6 no load 15a load f s = 350khz 15a load f s = 500khz oscillator frequency vs. input voltage max8543 toc06 input voltage (v) oscillator frequency (khz) 5.0 4.5 4.0 3.5 420 440 460 480 500 520 540 560 580 600 400 3.0 5.5 t a = +85 c t a = +25 c t a = -40 c r6 = 53.6k ? oscillator frequency vs. input voltage max8543 toc07 input voltage (v) oscillator frequency (khz) 11.5 9.5 7.5 520 540 560 580 600 620 640 660 680 700 500 5.5 13.5 r6 = 42.2k ? t a = +85 c t a = -40 c t a = +25 c typical operating characteristics (t a = +25?, unless otherwise noted.)
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp 8 _______________________________________________________________________________________ typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) max8544 step-load response 7.5a to 15a to 7.5a (5a/ s) max8543 toc08 v out i out 50mv/div ac-coupled 0 5a/div 10 s/div max8544 step-load response 1.5a to 15a to 1.5a (5a/ s) max8543 toc09 v out i out 100mv/div ac-coupled 0 5a/div 10 s/div max8544 power-up waveforms max8543 toc10 v in v pok 5v/div 0 10a/div 2ms/div v out i l 2v/div 5v/div max8544 power-down waveforms max8543 toc11 v in v pok 5v/div 0 10a/div 2ms/div v out i l 2v/div 2v/div max8543 power-up waveforms max8543 toc12 v in 2v/div 0 10a/div 2ms/div v out i l 1v/div max8543 power-down waveforms max8543 toc13 v in 2v/div 0 10a/div 2ms/div v out i l 1v/div
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp _______________________________________________________________________________________ 9 max8544 enable waveforms max8543 toc14 v en 5v/div 0 10a/div 2ms/div v out i l 2v/div v pok 5v/div fsync and synco waveforms max8543 toc15 v out 1v/div 5v/div 2 s/div v lx v synco 10v/div v fsync 5v/div short circuit and recovery max8543 toc16 v in 10v/div 12v 0 1ms/div v out i in 1v/div i l 10a/div 0 10a/div overvoltage protection with 15a load max8543 toc17 v out 5v/div 40 s/div v dh v dl 1v/div 10v/div 0v 0v 5v 5v prebiased startup (output prebiased at 1.5v) max8543 toc18 v in 5v/div 1ms/div v lx v dl 2.5v 10v/div v out 5v/div 500mv/div 1.5v typical operating characteristics (continued) (t a = +25?, unless otherwise noted.)
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp 10 ______________________________________________________________________________________ pin description pin max8543 max8544 name function 1 2 gnd ground. connect to the analog ground plane. 23ss soft-start. connect a 0.1? to 1? ceramic capacitor from ss to gnd. this capacitor sets the soft-start period during startup. see the startup and soft-start section. ss is internally pulled to gnd in shutdown. 3 4 comp compensation. connect to an external rc network to compensate the feedback loop. see the compensation design section. comp is internally pulled to gnd in shutdown. 45fb output feedback. connect to the center of a voltage-divider connected between out and gnd to set the output voltage. the fb threshold voltage is 0.8v. 56en enable. drive en logic high to enable the output, or drive logic low for shutdown. connect en to in for always-on operation. 6 7 cs- negative differential current-sensing input 7 8 cs+ positive differential current-sensing input 9 ilim1 8 ilim digital programmable current-limit input for inductor current sensing (v cs+ - v cs- ). see table 3. 9 12 pgnd power ground. connect to the power ground plane and to the source of the low-side external mosfets. connect pgnd to gnd at a single point. 10 13 dl low-side mosfet gate-driver output. connect to the gate of the low-side external mosfets. dl is pulled low in shutdown. 11 14 vl internal 5v linear-regulator output. connect a 1? to 10? ceramic capacitor from vl to pgnd. connect vl to in for v in less than 5.5v. vl provides power for bias and gate drive. 12 15 in input supply voltage. in is the input to the internal linear regulator. connect vl to in for v in less than 5.5v. bode plot, 600khz, 15a load max8543 toc19 1khz 1mhz 100khz 10khz 0db 10db/div 90 30 /div sweep time 10.000s bode plot, 600khz, no load max8543 toc20 1khz 1mhz 100khz 10khz 0db 90 30 /div sweep time 10.000s 10db/div typical operating characteristics (continued) (t a = +25?, unless otherwise noted.)
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp ______________________________________________________________________________________ 11 pin description (continued) pin max8543 max8544 name function 13 16 lx inductor connection 14 17 dh high-side mosfet gate-driver output. connect dh to the gate of the high-side external mosfets. dh is pulled low in shutdown. 15 18 bst boost capacitor connection. connect a 0.1? or larger ceramic capacitor from bst to lx. bst provides power for the high-side mosfet gate drive. 16 19 fsync frequency set and synchronization. connect a resistor from fsync to gnd to set the switching frequency or drive with a clock signal to synchronize between 160khz and 1.2mhz. see the switching frequency and synchronization section . 1 ilim2 analog programmable current-limit input for low-side mosfet (v lx - v pgnd ). connect a resistor from ilim2 to ground to set the overcurrent threshold. see the setting the current limits section. 10 mode current-limit operating-mode selection. connect mode to vl for latch-off current limit or connect to gnd for automatic-recovery current limit with the max8544. the max8543 always uses automatic-recovery current limit. ?1pok power-ok. pok is an open-drain output that is high impedance when the output is above 91% of its nominal regulation voltage. pok is pulled low when the output is out of regulation and when the part is in shutdown. to use pok as a logic-level signal, connect a pullup resistor from pok to the logic supply. 20 synco synchronization output. provides a clock output that is 180?out of phase with the rising edge of dh for out-of-phase synchronization of another max8544.
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp 12 ______________________________________________________________________________________ max8544eep ss comp mode synco pok vl gnd vl en lx ilim2 cs- cs+ pgnd dl bst dh in ilim1 fsync fb 9 19 6 2 3 4 5 10 1 11 20 7 8 12 13 18 d1 c1 c2 c4a c4b c4c vl vl 17 16 14 15 c3 c6a c6b sync out r6 r3 r1 r7 r9 pok r2 r8 d2 c5 c9 n3 n4 l1 v out = 2.5v up to 15a v in = (10.8v to 13.2v) n2 n1 c7 c8 on off sync in r4 r5 c11 c10 c12 figure 1. typical applications circuit with 12v (?0%) input, 2.5v output at up to 15a, and 600khz switching frequency
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp ______________________________________________________________________________________ 13 table 1. suggested components for figure 1 designation qty description c1 1 1? ?0%, 16v x5r ceramic capacitor (0603) panasonic ecj1vb1c105m or equivalent c2 1 10? ?0%, 6.3v x5r ceramic capacitor (0805) panasonic ecj2fb0j106m or taiyo yuden jmk212bj106mg c3 1 0.1? ?0%, 50v x7r ceramic capacitor (0603) tdk c1608x7r1h104kt or equivalent c4a, c4b, c4c 2 10? ?0%, 16v x5r ceramic capacitors (1206) panasonic ecj3yb1c106m or equivalent c5 1 0.22? ?0%, 10v x7r ceramic capacitor (0603) taiyo yuden lmk107bj224ka or equivalent c6a, c6b 2 180?, 4v aluminum poly spcaps panasonic eefue0g181xr c7 1 10pf, 50v c0g ceramic capacitor (0603) c8 1 220pf ?0%, 50v x7r ceramic capacitor (0603) c9, c10 2 0.47? ?0% x7r ceramic capacitors (0603) c11 1 100pf, 50v c0g ceramic capacitor (0603) c12 1 470? ?0%, 16v aluminum electrolytic capacitor rubycon 16mbz470m d1 1 100ma, 30v schottky diode (sot-323) central cmssh-3 d2 1 250ma, 100v switching diode (sot23) central cmpd914 l1 1 0.82?, 33a, 1.6m ? inductor vishay ihlp-5050fd-01 0.82? n1, n2 2 n-channel mosfets irf irf7821 n3, n4 2 n-channel mosfets irf irf7832 r1 1 17.4k ? ?% resistor (0603) r2 1 8.06k ? ?% resistor (0603) r3 1 220k ? ?% resistor (0603) r4, r5 2 1.3k ? ?% resistors (0603) r6 1 42.2k ? ?% resistor (0603) r7 1 90.9k ? ?% resistor (0603) r8 1 9.31k ? ?% resistor (0603) r9 1 100k ? ?% resistor (0603)
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp 14 ______________________________________________________________________________________ max8543 ss comp cs- gnd vl en lx fb cs+ pgnd dl bst dh in ilim fsync 8 16 5 1 2 3 4 6 7 9 10 15 d1 c1 c2 c4a c4b c4d in 14 13 11 12 c3 c6a c6b r6 r3 r1 r2 d2 c5 c9 r4 r5 n3 n4 l1 v out = 2.5v up to 15a v in = (3v to 3.6v) n2 n1 c7 c8 c4c on off sync in c12 c11 c10 figure 2. typical applications circuit with 3.3v (?0%) input, 2.5v output at up to 15a, and 500khz switching frequency
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp ______________________________________________________________________________________ 15 table 2. suggested components for figure 2 designation qty description c1 1 1? 10%, 16v x5r ceramic capacitor (0603) panasonic ecj1vb1c105k or equivalent c2 1 10? ?0%, 6.3v x5r ceramic capacitor (0805) panasonic ecj2fb0j106m or taiyo yuden jmk212bj106mg c3 1 0.1? ?0%, 50v x7r ceramic capacitor (0603) tdk c1608x7r1h104kt or equivalent c4a, c4b, c4c, c4d 4 10? ?0%, 16v x5r ceramic capacitors (1206) panasonic ecj3yb1c106m or equivalent c5 1 0.22? ?0%, 10v x7r ceramic capacitor (0603) taiyo yuden lmk107bj224ka or equivalent c6a, c6b 2 180?, 4v, 10m ? aluminum poly spcaps panasonic eefue0g181xr c7 1 12pf, 50v c0g ceramic capacitor (0603) c8 1 220pf ?0%, 50v x7r ceramic capacitor (0603) c9, c10 2 0.47? ?0% x7r ceramic capacitors (0603) c11 1 100pf, 50v c0g ceramic capacitor (0603) c12 1 470? ?0%, 6.3v poscap sanyo 6pb470m d1 1 100ma, 30v schottky diode (sot-323) central cmssh-3 d2 1 250ma, 100v switching diode (sot23) central cmpd914 l1 1 0.33?, 16a, 2m ? inductor (13 x 10 x 6.35) coilcraft do3316p-331hc n1, n2 2 n-channel mosfets vishay si4866dy n3, n4 2 n-channel mosfets vishay si4866dy r1 1 17.4k ? ?% resistor (0603) r2 1 8.06k ? ?% resistor (0603) r3 1 150k ? ?% resistor (0603) r4, r5 2 680 ? ?% resistors (0603) r6 1 53.6k ? ?% resistor (0603)
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp 16 ______________________________________________________________________________________ detailed description dc-dc converter control architecture the max8543/max8544 step-down controllers use a pwm, current-mode control scheme. an internal transconductance amplifier establishes an integrated error voltage. the heart of the pwm controller is an open-loop comparator that compares the integrated voltage-feedback signal against the amplified current- sense signal plus the slope-compensation ramp, which are summed into the main pwm comparator to pre- serve inner-loop stability and eliminate inductor stair- casing. at each rising edge of the internal clock, the high-side mosfet turns on until the pwm comparator trips or the maximum duty cycle is reached or the peak current limit is reached. during this on-time, current ramps up through the inductor, storing energy in a magnetic field and sourcing current to the output. the current-mode feedback system regulates the peak inductor current as a function of the output-voltage- error signal. the circuit acts as a switch-mode transconductance amplifier and pushes the output lc filter pole normally found in a voltage-mode pwm to a higher frequency. during the second half of the cycle, the high-side mosfet turns off and the low-side mosfet turns on. the inductor releases the stored energy as the current ramps down, providing current to the output. the out- put capacitor stores charge when the inductor current exceeds the required load current and discharges when the inductor current is lower, smoothing the volt- age across the load. under soft-overload conditions, when the peak inductor current exceeds the selected current limit (see the current-limit circuit section), the high-side mosfet is turned off immediately and the low-side mosfet is turned on and remains on to let the inductor current ramp down until the next clock cycle. under heavy-overload or short-circuit conditions, the valley foldback current limit is enabled to reduce power dissipation of external components. the max8543/max8544 operate in a forced-pwm mode. as a result, the controller maintains a constant switching frequency, regardless of load, to allow for easier filtering of the switching noise. internal 5v linear regulator (vl) all max8543/max8544 functions are powered from the on-chip, low-dropout, 5v linear regulator. connect a 1? to 10? ceramic capacitor from vl to pgnd. in applications where the input voltage is less than 5.5v, bypass the linear regulator by connecting vl to in. undervoltage lockout when vl drops below 2.62v, the max8543/max8544 assume that the supply voltage is too low for proper oper- ation, so the undervoltage-lockout (uvlo) circuitry inhibits switching and forces the dl and dh gate drivers low. when vl rises above 2.7v, the controller enters the startup sequence and then resumes normal operation. startup and soft-start the soft-start circuitry gradually ramps up the reference voltage to control the rate of rise of the step-down con- troller output and reduce input surge currents during startup. the soft-start period is determined by the value of the capacitor from ss to gnd. the soft-start time is approximately (33ms/?) x c ss . the max8543/max8544 also feature prebias startup; therefore, both external power mosfets are kept off if the voltage at fb is higher than that at ss. this allows the max8543/max8544 to start up into a prebiased output without pulling the output voltage down. before the max8543/max8544 can begin the soft-start and power-up sequence, the following conditions must be met: 1) v vl exceeds the 2.7v undervoltage-lockout threshold. 2) en is at logic high. 3) the thermal limit is not exceeded. enable the max8543/max8544 feature a low-power shutdown mode. a logic low at en shuts down the controller. during shutdown, the output is high impedance, and both dh and dl are low. shutdown reduces the quies- cent current (i q ) to less than 10?. a logic high at en enables the controller. synchronous-rectifier driver (dl) synchronous rectification reduces conduction losses in the rectifier by replacing the normal schottky catch diode with a low-resistance mosfet switch. the max8543/max8544 also use the synchronous rectifier to ensure proper startup of the boost gate-driver circuit and to provide the current-limit signal. the dl low-side gate-drive waveform is always the complement of the dh high-side gate-drive waveform (with controlled dead time to prevent cross-conduction or shoot- through). an adaptive dead-time circuit monitors the dl voltage and prevents the high-side mosfet from turn- ing on until dl is fully off. for the dead-time circuit to work properly, there must be a low-resistance, low- inductance path from the dl driver to the mosfet gate. otherwise, the sense circuitry in the max8543/ max8544 can interpret the mosfet gate as off when gate charge actually remains.
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp ______________________________________________________________________________________ 17 use very short, wide traces, about 10 to 20 squares (50 mils to 100 mils wide if the mosfet is 1in from the device) for the gate drive. the dead time at the other edge (dh turning off) also has an adaptive dead-time circuit operating in a similar manner. for both edges, there is an additional fixed dead time after the adaptive dead time expires. high-side gate-drive supply (bst) a flying capacitor boost circuit (figure 3) generates the gate-drive voltage for the high-side n-channel mosfet. the capacitor between bst and lx is charged from vl up to v vl minus the diode forward-voltage drop while the low-side mosfet is on. when the low-side mosfet is switched off, the stored voltage of the capacitor is stacked above lx to provide the necessary turn-on voltage (v gs ) for the high-side mosfet. the controller then closes an internal switch between bst and dh to turn the high-side mosfet on. current-sense amplifier the max8543/max8544 current-sense circuit amplifies the differential current-sense voltage (v cs+ - v cs- ). the gain of the current-sense amplifier is determined by the states of ilim and ilim1. this amplified current-sense signal and the internal slope-compensation signal are summed (v sum ) together and fed into the pwm com- parator? inverting input. the pwm comparator shuts off the high-side mosfet when v sum exceeds the integrated feedback voltage (v comp ). the differential current sense is also used to provide peak inductor current limiting. this current limit is more accurate than the valley current limit, which is measured across the low-side mosfet? on-resistance. current-limit circuit the max8543/max8544 use both valley foldback current limiting and peak constant current limiting, simultaneously (figure 4). the valley foldback current limit is used to reduce power dissipation of external components, mainly inductor and power mosfets, and upstream power source, when output is severely overloaded or short circuited. thus the circuit can withstand short-circuit conditions indefinitely without causing overheating of any component. the peak constant current limit sets the cur- rent-limit point more accurately since it does not have to suffer the wide variation of the low-side power mosfet? on-resistance due to tolerance and temperature. the valley current is sensed across the on-resistance of the low-side mosfet (v pgnd - v lx ). the valley current limit trips when the sensed current exceeds the valley current-limit threshold. the valley current limit recovers when the sensed current drops below the valley current- limit threshold (except when using the latch-off option with the max8544). set the minimum valley current-limit threshold, when the output voltage is at a nominal regulated value, higher than the maximum peak current-limit setting. with this method, the current-limit point accuracy is controlled by the peak current limit and is not interfered with by the wide variation of mosfet on-resistance. see the setting the current limits section for how to set these limits. the max8543 has a fixed valley current-limit threshold and fixed foldback ratio. the max8544 can select between an adjustable valley current-limit threshold with adjustable foldback ratio and a fixed valley current limit without foldback for latch-off. when latch-off is used (mode is connected to vl), set the current-limit threshold by only one resistor from ilim2 to gnd and make sure this threshold is higher than the maximum output current required by at least a 20% margin. cycle en or input power to reset the current-limit latch. the peak current limit is used to sense the inductor current, and is more accurate than the valley current limit since it does not depend upon the on-resistance of the low-side mosfet. the peak current can be measured across the resistance of the inductor for the highest efficiency, or alternatively, a current-sense resistor can be used for more accurate current sensing. the max8543/max8544 have four selectable peak current- limit thresholds that are selected using ilim (max8543) or ilim1 (max8544). see table 3 for the current-limit settings. for more information on the current limit, see the setting the current limits section. max8543/ max8544 bst in dh lx dl n n figure 3. the boost circuit provides voltage for the high-side mosfet gate drive.
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp 18 ______________________________________________________________________________________ switching frequency and synchronization the max8543/max8544 have an adjustable internal oscillator that can be set to any frequency from 200khz to 1mhz. to set the switching frequency, connect a resistor from fsync to gnd. calculate the resistor value from the following equation: the max8543/max8544 can also be synchronized to an external clock by connecting the clock signal to fsync. when using an external clock, select r fsync such that the free-running frequency is within ?0% of the clock fre- quency. in addition, the max8544 has a synchronization output (synco) that provides a clock signal that is 180 out-of-phase with the max8544 switching. synco is used to synchronize a second controller 180 out-of- phase with the first by connecting synco of the first con- troller to fsync of the second when the first controller operates in free-running mode. when the first controller is synchronized to an external clock, the external clock is inverted to generate synco. power-good signal (pok) pok is an open-drain output on the max8544 that moni- tors the output voltage. when the output is above 91% of its nominal regulation voltage, pok is high impedance. when the output drops below 91% of its nominal regula- tion voltage, pok is pulled low. pok is also pulled low when the max8544 is shut down. to use pok as a logic- level signal, connect a pullup resistor from pok to the logic-supply rail. thermal-overload protection thermal-overload protection limits total power dissipation in the max8543/max8544. when the junction tempera- ture exceeds t j = +160?, an internal thermal sensor shuts down the device, allowing the ic to cool. the ther- mal sensor turns the ic on again after the junction tem- perature cools by 15?, resulting in a pulsed output during continuous thermal-overload conditions. design procedure setting the output voltage to set the output voltage for the max8543/max8544, connect fb to the center of an external resistor-divider from the output to gnd (figure 5). select r2 between 8k ? and 24k ? ; then calculate r1 with the following equation: where v fb = 0.8v. r1 and r2 should be placed as close to the ic as possible. inductor selection there are several parameters that must be examined when determining which inductor is to be used: input volt- age, output voltage, load current, switching frequency, and lir. lir is the ratio of peak-to peak inductor current ripple to maximum dc load current. a higher lir value allows for a smaller inductor, but results in higher losses and higher output ripple. rr v v out fb 12 1 = ? ? ? ? ? ? ? r f ns k ns fsync s =? ? ? ? ? ? ? ? ? ? ? ? ? 1 2 240 1 14 18 ? . time inductor current i valley i load i peak figure 4. inductor-current waveform max8543/ max8544 r1 r2 lx fb figure 5. setting the output voltage with a resistor voltage- divider
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp ______________________________________________________________________________________ 19 a good compromise between size and efficiency is an lir of 0.3. once all the parameters are chosen, the inductor value is determined as follows: where f s is the switching frequency. choose a standard- value inductor close to the calculated value. the exact inductor value is not critical and can be adjusted to make trade-offs among size, cost, and efficiency. lower inductor values minimize size and cost, but they also increase the output ripple and reduce the efficiency due to higher peak currents. on the other hand, higher induc- tor values increase efficiency, but eventually resistive losses due to extra turns of wire exceed the benefit gained from lower ac current levels. this is especially true if the inductance is increased without also increas- ing the physical size of the inductor. find a low-loss inductor with the lowest possible dc resistance that fits the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 300khz. the chosen inductor? saturation current rating must exceed the peak inductor current determined as: setting the current limits valley current limit the valley current limit employs a current foldback scheme. the max8543 has a fixed valley current-limit threshold of 130mv, and a fixed foldback ratio (p fb ) of 23%. the foldback ratio is the current-limit threshold when the output is at 0v (output shorted to ground), divided by the threshold when the output is at its nominal regulated value. thus, the minimum output current limit (i lim ) and maximum short-circuit current (i sc ) is calculat- ed as: where r ds(on) is the maximum on-resistance of the low-side mosfet at the highest expected operating junction temperature, and i p-p is the inductor ripple cur- rent, calculated as: ensure that i lim is equal to or greater than the maxi- mum load current at peak current limit (see the peak current limit section): where 40mv is the maximum current-limit threshold when the output is shorted (v out = 0v). the max8544 has an adjustable valley current limit and can be selected for foldback with automatic recovery, or constant current with latch-up. to set the current limit for foldback mode, connect a resistor from ilim2 to the output (r fobk ), and another resistor from ilim2 to gnd (r ilim ). see figure 6. the values of r fobk and r ilim are calculated as follows: 1) first, select the percentage of foldback (p fb ). this percentage corresponds to the current limit when v out equals zero, divided by the current limit when v out equals a nominal voltage. a typical value of p fb is in the range of 15% to 40%. a lower value of p fb yields lower short-circuit current. the following equations are used to calculate r fobk and r ilim: where i valley is the value of the inductor valley current at maximum load (i load(max) - 1/2 i p-p ), and r ds(on) is the maximum on-resistance of the low-side mosfet at the highest operating junction temperature. r ri pr vri p ilim ds on valley fb fobk out ds on valley fb = ? () ? ? () [] 51 51 () () r pv ap fobk fb out fb = ? () 51 i v r i sc ds on pp =+ ? 004 2 . () i vv v flv pp in out out sin ? = ? () i v r i lim ds on pp =+ ? 011 2 . () ii lir i peak load max load max =+ () () 2 l vvv v f i lir out in out in s load max = ? () () max8544 r fobk r ilim lx out ilim2 figure 6. ilim2 resistor connections
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp 20 ______________________________________________________________________________________ 2) if the resulting value of r ilim is negative, either increase p fb or choose a low-side mosfet with a lower r ds(on) . the latter is preferred as it increas- es the efficiency and results in a lower short-circuit current. to set the constant current limit for the latch-up mode, only r ilim is used. the equation for r ilim below sets the current-limit threshold at 1.2 times the maximum- rated output current: similarly, i valley is the value of the inductor valley current at maximum load, r ds(on) is the maximum on- resistance of the low-side mosfet at the highest oper- ating junction temperature. peak current limit peak inductor current-limit threshold (v th ) has four possible settings through ilim (max8543) or ilim1 (max8544) as shown in table 3 below. the resulting current limit is calculated as: where r dc is either the dc resistance of the inductor or the value of the optional current-sense resistor. note that v ilim is a logic-level setting, and can allow a variation of ?.1 x v vl without affecting v th . to ensure maximum output current, use the minimum value of v th from each setting, and the maximum r dc values at the highest expected operating temperature. the dc resis- tance of the inductor? copper wire has a +0.22%/? temperature coefficient. to use the dc resistance of the output inductor for cur- rent sensing, an rc circuit is added (see figure 7). the rc time constant is set to be twice the inductor (l / r dc ) time constant. pick the value of r4 in the range of 470 ? to 2k ? , and then calculate the capacitor value from: c9 = 2l / (r dc r4). add a resistor (r5) equal in value to r4 to the cs- connection to minimize input-offset error. the equivalent current-sense resistance is equal to the dc resistance of the inductor (r dc ). to use a current-sense resistor, connect the resistor as shown in figure 8. since most current-sense resistors have inductance, the rc circuit is also required and is calculated in the same manner as inductor current sensing. place c11 close to cs+ and cs- pins to decouple the high-frequency noise pickup. place c10 (same value as c9) across r5 to aid in short- circuit recovery. i v r i lim th dc pp =? ? 2 r ir a ilim valley ds on = 12 1 . () table 3. ilim current-limit threshold settings v ilim recommended ilim connection v th min (mv) v th typ (mv) v th max (mv) 0 gnd 38.5 50 56.5 1/3 v vl voltage-divider: 100k ? from ilim/ilim1 to gnd 200k ? from ilim/ilim1 to vl 85.0 100 115.0 2/3 v vl voltage-divider: 200k ? from ilim/ilim1 to gnd 100k ? from ilim/ilim1 to vl 127.5 150 172.5 v vl vl 170.0 200 230.0 max8543/ max8544 c9 v out r4 r5 r3 l1 lx cs- cs+ c11 c10 figure 8. using a current-sense resistor max8543/ max8544 c9 v out r4 r5 l1 lx cs- cs+ c11 c10 figure 7. inductor r dc current sensing
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp ______________________________________________________________________________________ 21 mosfet selection the max8543/max8544 drive two or four external, logic-level, n-channel mosfets as the circuit switch elements. the key selection parameters are: 1) on-resistance (r ds(on) ): the lower, the better. 2) maximum drain-to-source voltage (v dss ): should be at least 20% higher than the input supply rail at the high-side mosfet? drain. 3) gate charges (q g , q gd , q gs ): the lower, the better. for a 3.3v input application, choose a mosfet with a rated r ds(on) at v gs = 2.5v. for a 5v input application, choose the mosfets with rated r ds(on) at v gs 4.5v. for a good compromise between efficiency and cost, choose the high-side mosfet (n1, n2) that has conduc- tion losses equal to the switching loss at nominal input voltage and output current. the selected low-side mosfet (n3, n4) must have an r ds(on) that satisfies the current-limit-setting condition above. ensure that the low- side mosfet does not spuriously turn on due to dv/dt caused by the high-side mosfet turning on as this would result in shoot-through current and degrade the efficiency. mosfets with a lower q gd / q gs ratio have higher immunity to dv/dt. for high-current applications, it is often preferable to parallel two mosfets rather than to use a single large mosfet. for proper thermal-management design, the power dis- sipation must be calculated at the desired maximum operating junction temperature, maximum output current, and worst-case input voltage (for the low-side mosfet, worst case is at v in(max) ; for the high-side mosfet, it could be either at v in(max) or v in(min) ). the high-side and low-side mosfets have different loss components due to the circuit operation. the low-side mosfet oper- ates as a zero-voltage switch; therefore, major losses are the channel-conduction loss (p lscc ) and the body- diode conduction loss (p lsdc ): use r ds(on) at t j(max) : where v f is the body-diode forward-voltage drop, t dt is the dead time between high-side and low-side switching transitions, and f s is the switching frequency. the high-side mosfet operates as a duty-cycle control switch and has the following major losses: the channel- conduction loss (p hscc ), the vi overlapping switching loss (p hssw ), and the drive loss (p hsdr ). the high-side mosfet does not have body-diode conduction loss because the diode never conducts current: use r ds(on) at t j(max) : where i gate is the average dh-driver output current capability determined by: where r ds(on)(hs) is the high-side mosfet driver? on-resistance (1 ? , typ) and r gate is the internal gate resistance of the mosfet ( 0.5 ? to 3 ? ): where v gs v vl. in addition to the losses above, allow about 20% more for additional losses due to mosfet output capacitances and low-side mosfet body-diode reverse-recovery charge dissipated in the high-side mosfet, but it is not well defined in the mosfet data sheet. refer to the mosfet data sheet for thermal resistance specifications to calculate the pc board area needed to maintain the desired maximum operating junction temperature with the above calculated power dissipations. to reduce emi caused by switching noise, add a 0.1? ceramic capacitor from the high-side switch drain to the low-side switch source or add resistors in series with dh and dl to slow down the switching transitions. however, adding series resistors increases the power dissipation of the mosfet, so be sure this does not overheat the mosfet. pqvf r rr hsdr g gs s gate gate ds on hs = + ()() i v rr gate vl ds on hs gate ? + 05 . ()() pvi qq i f hssw in load gs gd gate s = + p v v ir hscc out in load ds on = () 2 pivtf lsdc load f dt s = 2 p v v ir lscc out in load ds on =? ? ? ? ? ? ? 1 2 ()
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp 22 ______________________________________________________________________________________ mosfet snubber circuit fast switching transitions cause ringing because of res- onating circuit parasitic inductance and capacitance at the switching nodes. this high-frequency ringing occurs at lx? rising and falling transitions and can interfere with circuit performance and generate emi. to dampen this ringing, a series rc snubber circuit is added across each switch. below is the procedure for selecting the value of the series rc circuit. connect a scope probe to measure v lx to gnd and observe the ringing frequency, f r . find the capacitor value (connected from lx to gnd) that reduces the ringing frequency by half. the circuit parasitic capacitance (c par ) at lx is then equal to 1/3rd the value of the added capacitance above. the circuit parasitic inductance (l par ) is calculated by: the resistor for critical dampening (r snub ) is equal to 2 x f r x l par . adjust the resistor value up or down to tailor the desired damping and the peak voltage excursion. the capacitor (c snub ) should be at least 2 to 4 times the value of the c par to be effective. the power loss of the snubber circuit (p rsnub ) is dissipated in the resistor and can be calculated as: where v in is the input voltage and f sw is the switching frequency. choose an r snub power rating that meets the specific application? derating rule for the power dissipation calculated. input capacitor the input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit? switching. the input capacitor must meet the ripple-current requirement (i rms ) imposed by the switching currents defined by the following equation: i rms has a maximum value when the input voltage equals twice the output voltage (v in = 2 x v out ), so i rms(max) = i load / 2. ceramic capacitors are recommended due to their low esr and esl at high frequency with relatively low cost. choose a capacitor that exhibits less than 10? temperature rise at the maximum operating rms current for optimum long-term reliability. ceramic capacitors with an x5r or better temperature characteristic are recom- mended. when operating from a soft input source, an additional input capacitor (bulk bypass capacitor) may be required to prevent input from sagging. output capacitor the key selection parameters for the output capacitor are the actual capacitance value, the equivalent series resistance (esr), the equivalent series inductance (esl), and the voltage-rating requirements. these parameters affect the overall stability, output voltage ripple, and transient response. the output ripple has three components: variations in the charge stored in the output capacitor, the voltage drop across the capacitor? esr, and esl caused by the current into and out of the capacitor. the maximum output voltage ripple is estimated as follows: v ripple = v ripple(esr) + v ripple(c) + v ripple(esl) the output voltage ripple as a consequence of the esr, esl, and output capacitance is: where i p-p is the peak-to-peak inductor current: these equations are suitable for initial capacitor selec- tion, but final values should be chosen based on a proto- type or evaluation circuit. as a general rule, a smaller current ripple results in less output voltage ripple. since the inductor ripple current is a factor of the inductor value and input voltage, the output voltage ripple decreases with larger inductance, and increases with higher input voltages. polymer, tantalum, or aluminum electrolytic capacitors are recommended. i vv fl v v pp in out s out in ? = ? v i cf ripple c pp out s () = ? 8 v v l esl ripple esl in () = v i esr ripple esr p p () = ? i ivvv v rms load out in out in = ? () pcvf rsnub snub in sw = () 2 l fc par r par = () 1 2 2
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp ______________________________________________________________________________________ 23 the aluminum electrolytic capacitor is the least expen- sive; however, it has higher esr. to compensate for this, use a ceramic capacitor in parallel to reduce the switch- ing ripple and noise. for reliable and safe operation, ensure that the capacitor? voltage and ripple-current rat- ings exceed the calculated values. the response to a load transient depends on the selected output capacitors. after a load transient, the output voltage instantly changes by esr x ? i load . before the controller can respond, the output voltage deviates further depending on the inductor and output capacitor values. after a short period of time (see the typical operating characteristics ), the controller responds by regulating the output voltage back to its nominal state. the controller response time depends on its closed-loop bandwidth. with a higher bandwidth, the response time is faster, thus preventing the output voltage from further deviation from its regulation value. compensation design the max8543/max8544 use an internal transconduc- tance error amplifier whose output compensates the control loop. the external inductor, output capacitor, compensation resistor, and compensation capacitors determine the loop stability. the inductor and output capacitor are chosen based on performance, size, and cost. additionally, the compensation resistor and capaci- tors are selected to optimize control-loop stability. the component values, shown in the typical application circuits (figures 1 and 2), yield stable operation over the given range of input-to-output voltages. the controller uses a current-mode control scheme that regulates the output voltage by forcing the required cur- rent through the external inductor, so the max8543/ max8544 use the voltage drop across the dc resistance of the inductor or the alternate series current-sense resis- tor to measure the inductor current. current-mode control eliminates the double pole in the feedback loop caused by the inductor and output capacitor resulting in a smaller phase shift and requiring a less elaborate error-amplifier compensation than voltage-mode control. a simple single series r c and c c is all that is needed to have a stable, high-bandwidth loop in applications where ceramic capacitors are used for output filtering. for other types of capacitors, due to the higher capacitance and esr, the frequency of the zero created by the capacitance and esr is lower than the desired closed-loop crossover fre- quency. to stabilize a nonceramic output-capacitor loop, add another compensation capacitor (c f ) from comp to gnd to cancel this esr zero. the basic regulator loop is modeled as a power modu- lator, output feedback divider, and an error amplifier. the power modulator has dc gain set by g mc x r load , with a pole and zero pair set by r load , the output capacitor (c out ), and its esr. below are equations that define the power modulator: where r load = v out / i out(max) , f s is the switching frequency, l is the output inductance, and g mc = 1 / (a vcs r dc ), where a vcs is the gain of the cur- rent-sense amplifier and r dc is the dc resistance of the inductor (or current-sense resistor). a vcs is dependent on the current-limit selection at ilim, and ranges from 3 to 11 (see current-sense amplifier voltage gain in the electrical characteristics table ). the frequencies at which the pole and zero created by the power modulator are determined as follows: when c out is composed of ??identical capacitors in parallel, the resulting c out = n x c out(each) , and esr = esr (each) / n. note that the capacitor zero for a par- allel combination of like capacitors is the same as for an individual capacitor. the feedback voltage-divider has a gain of g fb = v fb / v out , where v fb is equal to 0.8v. the transconductance error amplifier has a dc gain, g ea(dc) = g mea x r o , where g mea is the error-amplifier transconductance, which is equal to 110?, r o is the output resistance of the error amplifier, which is 10m ? . a dominant pole is set by the compensation capacitor (c c ), the amplifier output resistance (r o ), and a zero is set by the compensation resistor (r c ) and the compen- sation capacitor (c c ). there is an optional pole set by c f and r c to cancel the output-capacitor esr zero if it occurs near the crossover frequency (f c ). thus: f crr pdea coc = + 1 2 () f c esr zmod out = 1 2 f c rfl rfl esr pmod out load s load s = + + ? ? ? ? ? ? 1 2 () gg rfl rfl mod dc mc load s load s () () = +
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp 24 ______________________________________________________________________________________ the crossover frequency, f c , should be much higher than the power-modulator pole f pmod . also, f c should be less than or equal to 1/5th the switching frequency. select a value for f c in the range: at the crossover frequency, the total loop gain must equal 1, and is expressed as: for the case where f zmod is greater than f c : then r c can be calculated as: where g mea = 110?. the error-amplifier compensation zero formed by r c and c c should be set at the modulator pole f pmod . c c is calculated by: if f zmod is less than 5 x f c , add a second capacitor c f from comp to gnd. the value of c f is calculated as follows: as the load current decreases, the modulator pole also decreases; however, the modulator gain increases accordingly and the crossover frequency remains the same. for the case where f zmod is less than f c : the power-modulator gain at f c is: the error-amplifier gain at f c is: r c is calculated as: where g mea = 110?. c c is calculated from: c f is calculated from: below is a numerical example to calculate r c and c c values of the typical operating circuit of figure 1 (max8544): a vcs = 11 (for ilim1 = gnd) r dc = 2.5m ? g mc = 1 / (a vcs x r dc ) = 1 / (11 x 0.0025) = 36.7s v out = 2.5v i out(max) = 15a r load = v out / i out(max) = 2.5 / 15 = 0.167 ? c out = 360? esr = 5m ? gg rfl rfl mod dc mc load s load s () () . .( ). .( ). . = + = () + () = ? ? 36 36 0 167 600 10 0 8 10 0 167 600 10 0 8 10 450 36 36 c rf f c zmod = 1 2 c rflc rflr c load s out load s c = + () () r v v f gg f c out fb c mea mod fc zmod = () ggr f f ea fc mea c zmod c () = gg f f mod fc mod dc pmod zmod () ( ) = c rf f c zmod = 1 2 c rflc rflr c load s out load s c = + () () r v gvg c out mea fb mod fc = () gg f f mod fc mod dc pmod c () ( ) = ggr ea fc mea c () = gg v v ea fc mod fc fb out () () = 1 ff f pmod c s << 5 f cr pea fc = 1 2 f cr zea cc = 1 2
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp ______________________________________________________________________________________ 25 3.43khz << f c < 120khz; select f c = 120khz. since f zmod < f c : select the nearest standard value: c c = 220pf select the nearest standard value: c f = 10pf: r3 = r c = 220k ? c8 = c c = 220pf c7 = c f = 10pf applications information pc board layout guidelines careful pc board layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention. follow these guidelines for good pc board layout: 1) place ic decoupling capacitors as close to ic pins as possible. keep separate the power ground plane and the signal ground plane. place the input ceramic decoupling capacitor directly across and as close as possible to the high-side mosfet? drain and the low-side mosfet? source. this is to help contain the high switching current within this small loop. 2) for output current greater than 10a, a four-layer pc board is recommended. pour a signal ground plane in the second layer underneath the ic to min- imize noise coupling. 3) connect input, output, snubber, and vl capacitors to the power ground plane; connect all other capacitors to the signal ground plane. 4) place the inductor current-sense resistor and capaci- tor as close to the inductor as possible. make a kelvin connection to minimize the effect of pc board trace resistance. place the input bias balance resistor and bypass capacitor (r5 and c10 in figures 7 and 8) near cs-. run two closely parallel traces from across the capacitor (c9 in figures 7 and 8) to cs+ and cs-. place the decoupling capacitor c11 close to cs+ and cs- pins. 5) place the mosfet as close as possible to the ic to minimize trace inductance of the gate-drive loop. if parallel mosfets are used, keep the trace lengths to both gates equal. 6) connect the drain leads of the power mosfet to a large copper area to help cool the device. refer to the power mosfet data sheet for recommended copper area. 7) place the feedback and compensation components as close to the ic pins as possible. connect the feedback-divider resistor from fb to the output as close as possible to the farthest output capacitor. refer to the max8544 evaluation kit for an example layout. c rf pf f c zmod = = = 1 2 1 2 220 10 88 4 10 82 33 ()(.) . c rflc rflr pf c load s out load s c = + () = + ? ? ? ? = ?? ? .( )(. )( ) .( )(. )( ) 0 167 600 10 0 8 10 360 10 0 167 600 10 0 8 10 220 10 202 36 6 36 3 r v v f gg f k c out fb c mea mod fc zmod = = = ? () . . ().(.) 25 08 120 10 110 10 0 175 88 4 10 220 3 63 ? gg f f mod fc mod dc pmod zmod () ( ) . . . . = = = 45 343 10 88 4 10 0 175 3 3 f c esr khz zmod out = = = ? 1 2 1 2 360 10 0 005 88 4 6 (). . ff f pmod c s << 5 f c rfl rfl esr khz pmod out load s load s = + + ? ? ? ? ? ? = ? ? ? ? + ? ? ? ? + ? ? ? ? ? ? ? ? ? ? = ? ? ? 1 2 1 2 360 10 0 167 600 10 0 8 10 0 167 600 10 0 8 10 0 005 343 6 36 36 () .( ). .( ). . .
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp 26 ______________________________________________________________________________________ table 4. suggested component manufacturers manufacturer component website phone central semiconductor diodes www.centralsemi.com 631-435-1110 coilcraft inductors www.coilcraft.com 800-322-2645 international rectifier mosfets www.irf.com 310-322-3331 kamaya resistors www.kamaya.com 260-489-1533 panasonic capacitors www.panasonic.com 714-373-7366 sanyo capacitors www.sanyo.com 619-661-6835 sumida inductors www.sumida.com 847-956-0666 taiyo yuden capacitors www.t-yuden.com 408-573-4150 tdk capacitors www.component.tdk.com 847-803-6100 vishay/siliconix mosfets www.vishay.com 402-564-3131 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 gnd fsync bst dh lx in vl dl pgnd top view max8543 ss comp cs- fb en cs+ ilim 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 synco fsync bst dh comp ss gnd ilim2 lx in vl dl cs+ cs- en fb 12 11 9 10 pgnd pok mode ilim1 max8544 pin configurations chip information transistor count: 4185 process: bicmos
max8543/max8544 step-down controllers with prebias startup, lossless sensing, synchronization, and ovp maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 27 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qsop.eps e 1 1 21-0055 package outline, qsop .150", .025" lead pitch

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